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Question 1 of 60 Quiz ID: q1

What is the fundamental requirement for a program to be executed?

It must be compiled into machine code

It must be brought from disk into memory and placed within a process

It must be stored in cache memory

It must be loaded into virtual memory only

Question 2 of 60 Quiz ID: q2

Which storage types can the CPU access directly?

Main memory and disk storage

Cache and disk storage

Main memory and registers only

Virtual memory and cache

Question 3 of 60 Quiz ID: q3

What is the typical access time for CPU registers compared to main memory?

Registers take many cycles, memory takes one cycle

Both take the same amount of time

Registers take one CPU clock or less, memory can take many cycles

Memory is always faster than registers

Question 4 of 60 Quiz ID: q4

What sits between main memory and CPU registers to improve performance?

Virtual memory

Cache

Disk storage

Translation lookaside buffer

Question 5 of 60 Quiz ID: q5

How is memory protection implemented using base and limit registers?

Base register contains the largest address, limit contains the smallest

Base register contains the smallest physical address, limit contains the range of logical addresses

Both registers contain the same value

Base register is for reading, limit register is for writing

Question 6 of 60 Quiz ID: q6

What must the CPU check for every memory access in user mode?

That the access is within the cache

That the access is between base and limit for that user

That the access is to virtual memory only

That the access is to read-only memory

Question 7 of 60 Quiz ID: q7

When does compile-time address binding occur?

When the process is loaded into memory

When the process is executed

When memory location is known a priori and absolute code can be generated

When the process moves during execution

Question 8 of 60 Quiz ID: q8

What type of code must be generated if memory location is not known at compile time?

Absolute code

Relocatable code

Static code

Fixed code

Question 9 of 60 Quiz ID: q9

When does execution-time address binding require hardware support?

Never

Always

When the process can be moved during execution from one memory segment to another

Only during compilation

Question 10 of 60 Quiz ID: q10

What is a logical address?

Address seen by the memory unit

Address generated by the CPU, also referred to as virtual address

Physical location in memory

Address used by the disk controller

Question 11 of 60 Quiz ID: q11

When are logical and physical addresses the same?

Always

Never

In compile-time and load-time address-binding schemes

Only in execution-time address-binding schemes

Question 12 of 60 Quiz ID: q12

What is the Memory Management Unit (MMU)?

Software that manages memory allocation

Hardware device that maps virtual to physical address at run time

A type of cache memory

The main memory controller

Question 13 of 60 Quiz ID: q13

In the simple MMU scheme, what is the base register called?

Base register

Limit register

Relocation register

Translation register

Question 14 of 60 Quiz ID: q14

How does the relocation register work?

It stores the size of the process

Its value is added to every address generated by a user process when sent to memory

It prevents memory access

It stores the process ID

Question 15 of 60 Quiz ID: q15

What is dynamic loading?

Loading the entire program into memory at once

A routine is not loaded until it is called

Loading programs from cache

Loading programs into virtual memory only

Question 16 of 60 Quiz ID: q16

What is the main advantage of dynamic loading?

Faster program execution

Better memory-space utilization; unused routines are never loaded

Reduced compilation time

Simpler program structure

Question 17 of 60 Quiz ID: q17

What is static linking?

Linking postponed until execution time

System libraries and program code combined by the loader into the binary program image

Linking that occurs during runtime

Linking that uses stubs

Question 18 of 60 Quiz ID: q18

In dynamic linking, what is a stub?

A complete library routine

Small piece of code used to locate the appropriate memory-resident library routine

A type of memory protection

A cache entry

Question 19 of 60 Quiz ID: q19

How is main memory typically partitioned in contiguous allocation?

All memory for user processes only

Resident OS in high memory, user processes in low memory

Resident OS in low memory with interrupt vector, user processes in high memory

Random allocation throughout memory

Question 20 of 60 Quiz ID: q20

What is a hole in the context of variable partition allocation?

A corrupted memory location

A block of available memory

A protected memory area

A cache miss

Question 21 of 60 Quiz ID: q21

Which dynamic storage allocation strategy allocates the first hole that is big enough?

Best-fit

Worst-fit

First-fit

Next-fit

Question 22 of 60 Quiz ID: q22

Which allocation strategy produces the smallest leftover hole?

First-fit

Best-fit

Worst-fit

Random-fit

Question 23 of 60 Quiz ID: q23

What is external fragmentation?

Memory internal to a partition that is not being used

Total memory space exists to satisfy a request, but it is not contiguous

Memory that is corrupted

Memory that cannot be accessed

Question 24 of 60 Quiz ID: q24

What is internal fragmentation?

Total memory space is not contiguous

Allocated memory may be slightly larger than requested memory

Memory that is shared between processes

Memory that is swapped to disk

Question 25 of 60 Quiz ID: q25

According to the 50-percent rule, what fraction of memory may be unusable due to fragmentation?

1/4

1/3

1/2

2/3

Question 26 of 60 Quiz ID: q26

What is compaction in memory management?

Reducing the size of programs

Shuffling memory contents to place all free memory together in one large block

Compressing data in memory

Removing unused programs from memory

Question 27 of 60 Quiz ID: q27

What are the fixed-sized blocks of physical memory called in paging?

Pages

Segments

Frames

Blocks

Question 28 of 60 Quiz ID: q28

What are the fixed-sized blocks of logical memory called in paging?

Frames

Pages

Segments

Partitions

Question 29 of 60 Quiz ID: q29

What is the typical size range for page/frame sizes?

64 bytes to 1 KB

512 bytes to 16 MB

1 KB to 4 KB only

16 MB to 1 GB

Question 30 of 60 Quiz ID: q30

How is a logical address divided in paging?

Base address and offset

Segment number and offset

Page number and page offset

Frame number and frame offset

Question 31 of 60 Quiz ID: q31

If the logical address space is 2^m and page size is 2^n, how many bits are used for the page number?

n bits

m bits

m-n bits

m+n bits

Question 32 of 60 Quiz ID: q32

In the paging example with page size = 2,048 bytes and process size = 72,766 bytes, what is the internal fragmentation?

1,086 bytes

962 bytes

2,048 bytes

1,024 bytes

Question 33 of 60 Quiz ID: q33

What is the average internal fragmentation for paging?

1 frame

1/4 frame size

1/2 frame size

1 frame - 1 byte

Question 34 of 60 Quiz ID: q34

Where is the page table kept?

In CPU registers

In cache memory

In main memory

On disk

Question 35 of 60 Quiz ID: q35

What does PTBR stand for?

Page Table Base Register

Page Translation Buffer Register

Physical Table Base Register

Process Table Base Register

Question 36 of 60 Quiz ID: q36

What is the main problem with keeping the page table in main memory?

It takes too much space

Every data/instruction access requires two memory accesses

It cannot be protected

It is too slow to update

Question 37 of 60 Quiz ID: q37

What does TLB stand for?

Translation Lookaside Buffer

Table Lookup Buffer

Translation Logic Block

Table Location Buffer

Question 38 of 60 Quiz ID: q38

What is the typical size range for TLBs?

32 to 128 entries

64 to 1,024 entries

1,024 to 4,096 entries

4,096 to 16,384 entries

Question 39 of 60 Quiz ID: q39

With an 80% TLB hit ratio and 10 ns memory access time, what is the Effective Access Time?

10 ns

12 ns

15 ns

20 ns

Question 40 of 60 Quiz ID: q40

What does a valid bit in a page table entry indicate?

The page is in cache

The page is in the process' logical address space and is a legal page

The page is read-only

The page is shared

Question 41 of 60 Quiz ID: q41

What type of code can be shared among processes?

Any code

Read-only (reentrant) code

Process-specific code

Interrupt handlers only

Question 42 of 60 Quiz ID: q42

For a 32-bit logical address space with 4KB pages, how many page table entries are needed?

1,024 entries

4,096 entries

1 million entries

4 million entries

Question 43 of 60 Quiz ID: q43

If each page table entry is 4 bytes, how much memory is needed for the page table in the above scenario?

4 KB

1 MB

4 MB

16 MB

Question 44 of 60 Quiz ID: q44

In a two-level paging scheme with 32-bit addresses and 4K pages, how is the 20-bit page number divided?

15-bit page number, 5-bit offset

10-bit page number, 10-bit offset

12-bit page number, 8-bit offset

8-bit page number, 12-bit offset

Question 45 of 60 Quiz ID: q45

What is p1 in the two-level paging address format p1|p2|d?

Index into the inner page table

Index into the outer page table

Page offset

Frame number

Question 46 of 60 Quiz ID: q46

Why is two-level paging insufficient for 64-bit address spaces?

Too slow

The outer page table would still be too large

Not enough memory

Hardware limitations

Question 47 of 60 Quiz ID: q47

What is the main idea behind hashed page tables?

Store pages in hash order

The virtual page number is hashed into a page table

Use hash functions for encryption

Compress page table entries

Question 48 of 60 Quiz ID: q48

What does each element in a hashed page table contain?

Only the frame number

Only the virtual page number

Virtual page number, mapped page frame value, and pointer to next element

Only a pointer to the next element

Question 49 of 60 Quiz ID: q49

What is the main advantage of inverted page tables?

Faster access time

Decreases memory needed to store each page table

Better security

Easier implementation

Question 50 of 60 Quiz ID: q50

What is swapping?

Moving data between cache and memory

A process can be swapped temporarily out of memory to a backing store

Moving pages between physical frames

Exchanging data between processes

Question 51 of 60 Quiz ID: q51

What is the backing store in swapping?

Main memory

CPU cache

Fast disk large enough to accommodate copies of all memory images

Virtual memory

Question 52 of 60 Quiz ID: q52

For a 100MB process with 50MB/sec transfer rate, what is the swap out time?

1000 ms

2000 ms

4000 ms

500 ms

Question 53 of 60 Quiz ID: q53

Why is standard swapping not used in modern operating systems?

Too complex to implement

Hardware limitations

Context switch time can be very high

Security concerns

Question 54 of 60 Quiz ID: q54

Why don't mobile systems typically support swapping?

Insufficient CPU power

Flash memory has small space, limited write cycles, and poor throughput

Battery life concerns

Security restrictions

Question 55 of 60 Quiz ID: q55

What does iOS do when memory is low?

Crashes the system

Asks apps to voluntarily relinquish allocated memory

Automatically swaps to disk

Restarts all applications

Question 56 of 60 Quiz ID: q56

What is the IA-32 architecture?

64-bit Intel architecture

32-bit Pentium CPU architecture

ARM mobile architecture

SPARC architecture

Question 57 of 60 Quiz ID: q57

How many segments can each process have in IA-32 architecture?

Up to 8K segments

Up to 16K segments

Up to 32K segments

Unlimited segments

Question 58 of 60 Quiz ID: q58

What are the possible page sizes in Intel IA-32 architecture?

4 KB only

4 KB or 2 MB

4 KB or 4 MB

2 MB or 4 MB

Question 59 of 60 Quiz ID: q59

What is the addressing limit that led Intel to create Page Address Extension (PAE)?

16-bit address limits

32-bit address limits

64-bit address limits

8-bit address limits

Question 60 of 60 Quiz ID: q60

In ARM architecture, what are the two types of TLBs used?

Data TLB and instruction TLB only

Outer level micro TLBs and inner main TLB

Primary and secondary TLBs

User TLB and kernel TLB

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