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Question 1 of 40 Quiz ID: q1

In the CPU block diagram presented, which component is directly responsible for modifying the Program Counter?

Instruction Decoder

ALU

Literal Address Operation section

Timing, Control and Register selection unit

Question 2 of 40 Quiz ID: q2

What is the primary function of the 'Timing, Control and Register selection' unit in the CPU diagram?

To perform arithmetic and logic operations

To manage the flow of data between the clock, interrupts, and all other CPU sections

To decode instructions from the Instruction Register

To store temporary data for the ALU

Question 3 of 40 Quiz ID: q3

According to the lecture, what are the three main categories of CPU performance enhancements discussed?

Caching, Prefetching, Speculative Execution

Pipelining, Parallelism, Advanced processor architectures

Multithreading, Multicore, Superscalar

Clock Speed Increase, Larger Registers, Faster RAM

Question 4 of 40 Quiz ID: q4

In the sequential laundry analogy, what is the total time taken to complete one load (wash, dry, fold)?

30 minutes

40 minutes

90 minutes

20 minutes

Question 5 of 40 Quiz ID: q5

What is the throughput improvement for 4 loads when moving from sequential to pipelined laundry?

Throughput is halved

Throughput remains the same

Throughput is nearly doubled

Throughput is quadrupled

Question 6 of 40 Quiz ID: q6

The pipelined laundry example demonstrates that the overall pipeline rate is limited by:

The fastest stage

The average of all stage times

The slowest stage

The number of tasks

Question 7 of 40 Quiz ID: q7

What is the 'time to fill' the pipeline also known as?

Drain time

Latency

Throughput penalty

Pipeline startup cost

Question 8 of 40 Quiz ID: q8

In a CPU pipeline, what is the primary metric for improvement?

Reducing the latency of a single instruction

Increasing the clock speed of the slowest stage

Improving the throughput of the entire workload

Minimizing the number of pipeline stages

Question 9 of 40 Quiz ID: q9

In the 5-stage MIPS pipeline (IF, ID, EX, MEM, WB), which stage is responsible for calculating a memory address?

Instruction Fetch (IF)

Instruction Decode (ID)

Execute (EX)

Memory Access (MEM)

Question 10 of 40 Quiz ID: q10

How many clock cycles does it take for a single instruction to complete (latency) in a 5-stage pipeline?

1 cycle

3 cycles

5 cycles

It depends on the instruction

Question 11 of 40 Quiz ID: q11

In the ideal pipelined execution diagram, what is happening in Cycle 4?

Only Instruction 1 is executing (EX)

Instruction 1 is writing back (WB), Instruction 2 is in MEM, Instruction 3 is in EX, Instruction 4 is in ID

Instruction 1 is in MEM, Instruction 2 is in EX, Instruction 3 is in ID, Instruction 4 is in IF

The pipeline is still being filled

Question 12 of 40 Quiz ID: q12

What is the primary purpose of the pipeline registers (e.g., between IF/ID, ID/EX) in a CPU pipeline?

To store the final results of computations

To act as a permanent storage for frequently used data

To hold the output of one stage as the input for the next stage on the next clock cycle

To decode instructions before they are executed

Question 13 of 40 Quiz ID: q13

According to the Intel x86 history chart, which microarchitecture had a pipeline depth of 5 stages?

Pentium MMX (P55C)

Original Pentium (P5 / P54C)

Intel P6 Family

Bonnell (Atom)

Question 14 of 40 Quiz ID: q14

What trend is observable in the misprediction penalty for the Intel Core microarchitectures listed (Core, Core 2, Nehalem)?

It consistently decreases

It remains constant at 7

It consistently increases

It fluctuates randomly

Question 15 of 40 Quiz ID: q15

The Bonnell (Atom) microarchitecture pipeline has many small stages (IF1, IF2, ID1, ID2, etc.). What is a potential disadvantage of this design?

Lower maximum clock speed

Increased complexity and power consumption per instruction

Decreased misprediction penalty

Reduced number of instructions in flight

Question 16 of 40 Quiz ID: q16

In the 'Pipeline With a Branch Penalty' example, what causes the pipeline to stall or introduce bubbles?

A data dependency between instructions

A cache miss during instruction fetch

A taken branch instruction

An arithmetic overflow exception

Question 17 of 40 Quiz ID: q17

In the branch penalty diagram, how many clock cycles (CC) is the penalty for the taken branch?

1 CC

2 CC

3 CC

4 CC

Question 18 of 40 Quiz ID: q18

Looking at the branch penalty timing diagram, in which clock cycle is the branch instruction (Inst. 1) in its Execute (IE) stage?

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Question 19 of 40 Quiz ID: q19

After the branch is taken in the example, which instruction is fetched next?

Inst. 2

Inst. 3

Inst. 4

Inst. 20

Question 20 of 40 Quiz ID: q20

What fundamental CPU design concept is the laundry analogy primarily used to explain?

Virtual Memory

Pipelining

Cache Hierarchies

Multicore Processing

Question 21 of 40 Quiz ID: q21

In the CPU block diagram, which bus is likely used to transfer data from the 'RAM & Data Registers' to the 'ALU'?

Address Bus

External System Bus

Internal Data Bus

Control Bus

Question 22 of 40 Quiz ID: q22

Which component in the CPU diagram is responsible for holding the current instruction being decoded?

Program Counter

Accumulator

Instruction Register

Address Register

Question 23 of 40 Quiz ID: q23

What is the role of the 'FLAG & Special Function Registers' shown in the diagram?

To store the address of the next instruction

To hold temporary data for the ALU

To store status bits (e.g., zero, carry) and control information from ALU operations

To decode instruction opcodes

Question 24 of 40 Quiz ID: q24

The potential speedup from pipelining is theoretically equal to what?

The number of tasks

The time of the longest stage

The number of pipeline stages

The sum of all stage times

Question 25 of 40 Quiz ID: q25

Why does 'time to drain/flush' the pipeline reduce the overall speedup?

It requires extra energy to stop the pipeline

It prevents new tasks from entering the pipeline

It represents cycles where the pipeline is not full, reducing average throughput

It causes errors in the final results of tasks

Question 26 of 40 Quiz ID: q26

In the 5-stage pipeline notation (IF, ID, EX, MEM, WB), what is a common primary activity of the 'ID' stage?

Perform an arithmetic operation

Read operands from the register file

Access data memory

Write a result to the register file

Question 27 of 40 Quiz ID: q27

Which stage in a standard 5-stage RISC pipeline is often idle for instructions that do not access memory (e.g., ADD, XOR)?

IF

ID

EX

MEM

WB

Question 28 of 40 Quiz ID: q28

Comparing Pentium and Pentium MMX pipelines, what was a consequence of adding the MMX execution stages?

The overall pipeline depth decreased

The misprediction penalty decreased

The pipeline became deeper for MMX multiply operations

The clock speed was forced to decrease

Question 29 of 40 Quiz ID: q29

What does a larger branch misprediction penalty imply for a software developer?

The developer doesn't need to worry about branches

The cost of a poorly predicted branch is higher

Branches will be predicted with 100% accuracy

The CPU has a smaller cache

Question 30 of 40 Quiz ID: q30

The Intel P6 family pipeline includes stages like 'Rename' and 'Schedule'. What advanced architecture concept do these stages facilitate?

Pipelining

Out-of-Order Execution

Speculative Execution

Caching

Question 31 of 40 Quiz ID: q31

In the branch penalty diagram, what is happening in clock cycle 5?

Inst. 1 is writing back, Inst. 20 is being fetched

The pipeline is completely stalled

Inst. 4 is executing, Inst. 20 is decoding

Inst. 1 is executing, Inst. 2 is decoding

Question 32 of 40 Quiz ID: q32

What is the state of the pipeline stages during the 'branch penalty' clock cycle?

They are powered down to save energy

They are processing incorrect instructions that will be flushed

They are stalled, performing no useful work (bubbles)

They are calculating the target address of the branch

Question 33 of 40 Quiz ID: q33

Which performance enhancement technique is characterized by executing multiple instructions simultaneously in the same clock cycle?

Pipelining

Superscalar Execution

Very Long Instruction Word (VLIW)

Both 2 and 3

Question 34 of 40 Quiz ID: q34

What is a 'structural hazard' in a pipelined processor?

A branch is mispredicted

An instruction needs data produced by a previous instruction that isn't ready

Two instructions in the pipeline need to use the same hardware resource at the same time

The program counter increments incorrectly

Question 35 of 40 Quiz ID: q35

What is a 'data hazard' in a pipelined processor?

A branch is mispredicted

An instruction needs data produced by a previous instruction that isn't ready

Two instructions in the pipeline need to use the same hardware resource at the same time

The program counter increments incorrectly

Question 36 of 40 Quiz ID: q36

What is a 'control hazard' in a pipelined processor?

A branch is mispredicted

An instruction needs data produced by a previous instruction that isn't ready

Two instructions in the pipeline need to use the same hardware resource at the same time

The program counter increments incorrectly

Question 37 of 40 Quiz ID: q37

Which technique is commonly used to reduce the impact of data hazards?

Branch Prediction

Forwarding (Bypassing)

Instruction Prefetching

Register Renaming

Question 38 of 40 Quiz ID: q38

The concept of 'Instruction Level Parallelism (ILP)' refers to:

Using multiple CPU cores to run different programs

The ability of a processor to execute multiple instructions from a single thread simultaneously

Adding more stages to the pipeline

Increasing the width of the data bus

Question 39 of 40 Quiz ID: q39

What is the fundamental difference between the 'Parallelism' and 'Pipelining' categories mentioned in the introduction?

Pipelining is for latency, Parallelism is for throughput

Pipelining is a form of temporal parallelism, while other forms (e.g., superscalar) involve spatial parallelism

They are the same concept

Pipelining is used in GPUs, Parallelism is used in CPUs

Question 40 of 40 Quiz ID: q40

Why is the 'Execute' stage in a pipeline often subdivided in complex CPUs like those in the Intel chart?

To reduce the cost of branch misprediction

To allow for a higher clock frequency by simplifying the work done per cycle

To make the instruction decoder simpler

To reduce the number of transistors needed

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