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Question 1 of 40 Quiz ID: q1

What is the sequence of signals activated on the buses when the CPU reads from memory?

Address on Address Bus, then RD signal, then data on Data Bus

RD signal, then Address on Address Bus, then data on Data Bus

Data on Data Bus, then Address on Address Bus, then RD signal

Address on Address Bus, then data on Data Bus, then RD signal

Question 2 of 40 Quiz ID: q2

What is the primary role of a Memory Controller in a system?

To execute arithmetic operations for the CPU

To manage communication between the CPU and different memory modules

To store the BIOS and boot instructions

To increase the clock speed of the CPU

Question 3 of 40 Quiz ID: q3

In the instruction `Add R4,100(R1)`, what is the effective address?

The address stored in register R4

The immediate value 100

The sum of 100 and the value stored in register R1

The address stored in register R1

Question 4 of 40 Quiz ID: q4

Which addressing mode is primarily used for implementing a stack structure using push and pop operations?

Direct Addressing

Autoincrement Addressing

Autodecrement Addressing

Indexed Addressing

Question 5 of 40 Quiz ID: q5

The ever-widening gap between processor and memory performance, growing roughly 50% per year, is often called the:

Memory Bottleneck

Processor-Memory Gap

Von Neumann Limitation

Access Time Dilemma

Question 6 of 40 Quiz ID: q6

What is the fundamental economic and physical reason for implementing a memory hierarchy?

To make the CPU run hotter

To create the illusion of a large, fast, and cheap memory

To simplify compiler design

To reduce the number of pins on the CPU

Question 7 of 40 Quiz ID: q7

According to the principle of locality, which of these is an example of *temporal* locality?

Accessing consecutive elements of an array

Executing instructions in a loop repeatedly

Accessing variables declared near each other

Reading a function's instructions sequentially

Question 8 of 40 Quiz ID: q8

In a typical desktop memory hierarchy, which level is generally the largest and slowest form of semiconductor memory directly accessible by the CPU?

L1 Cache

L2 Cache

L3 Cache

Main Memory (DRAM)

Question 9 of 40 Quiz ID: q9

Why would the first code snippet (row-major order) likely be faster than the second (column-major order) for a matrix stored in row-major order?

It has fewer lines of code

It uses a different algorithm

It exhibits better spatial locality

It has a lower instruction count

Question 10 of 40 Quiz ID: q10

What does the 'Inclusion Property' in a memory hierarchy typically refer to?

All data in a higher-level cache must also be in all lower-level caches

All data in a lower-level memory is a superset of the data in higher-level memories

The cost of memory must be included in the processor's price

The hit rate must always be included in the miss rate calculation

Question 11 of 40 Quiz ID: q11

What is the 'Miss Penalty' in the context of a cache?

The time it takes to check if a block is in the cache

The rate at which cache accesses result in a miss

The time to replace a cache block and deliver the requested data to the processor

The size of the data block that was missed

Question 12 of 40 Quiz ID: q12

Which memory technology is characterized by being volatile, having the lowest cost per bit, and using a storage capacitor that requires periodic refreshing?

SRAM (Static RAM)

DRAM (Dynamic RAM)

ROM (Read-Only Memory)

Flash Memory

Question 13 of 40 Quiz ID: q13

What is a key hardware difference between a DRAM cell and an SRAM cell that contributes to SRAM's speed?

SRAM uses a capacitor, DRAM uses a transistor

SRAM uses a flip-flop (multiple transistors), DRAM uses a capacitor and transistor

SRAM is optically erased, DRAM is electrically erased

SRAM must be refreshed, DRAM does not

Question 14 of 40 Quiz ID: q14

Which type of memory is non-volatile and allows for byte-level erasure and writing?

EPROM

EEPROM

PROM

Flash Memory

Question 15 of 40 Quiz ID: q15

What is the primary material used to construct a cache memory?

DRAM because of its high density

SRAM because of its speed

Flash memory because it is non-volatile

Magnetic disk because of its capacity

Question 16 of 40 Quiz ID: q16

In a direct-mapped cache, how is the location for a memory block determined?

It can be placed in any available cache block

It is chosen by a complex LRU algorithm

It can be placed in any block within a specific 'set'

It is mapped to one and only one specific cache block

Question 17 of 40 Quiz ID: q17

What is the main advantage of a fully associative cache mapping?

It is very simple and cheap to implement

It has the lowest possible conflict miss rate

It requires no tags to be stored

It uses a very fast linear search

Question 18 of 40 Quiz ID: q18

In an n-way set associative cache, a memory block can be placed in:

Exactly one specific block in the cache

Any block in the entire cache

Any block within one specific set, which contains n blocks

The first available block found

Question 19 of 40 Quiz ID: q19

Which cache replacement policy requires tracking the exact order in which blocks within a set were accessed?

Random Replacement

First-In-First-Out (FIFO)

Least Recently Used (LRU)

Least Frequently Used (LFU)

Question 20 of 40 Quiz ID: q20

What is the formula for Average Memory Access Time (AMAT)?

AMAT = Hit Time + Miss Rate

AMAT = Hit Time + Miss Rate * Miss Penalty

AMAT = Miss Penalty / Hit Time

AMAT = (Hit Time + Miss Penalty) * Miss Rate

Question 21 of 40 Quiz ID: q21

A CPU has a 95% instruction cache hit rate and a 90% data cache hit rate. If 20% of instructions are data-accessing loads/stores, what is the overall cache hit rate?

92.5%

93.0%

94.0%

95.0%

Question 22 of 40 Quiz ID: q22

When a cache miss occurs, what is the minimum unit of data that is transferred from main memory to the cache?

A single word (e.g., 4 bytes)

A block (or line), which is multiple words

An entire memory page (e.g., 4 KB)

A single byte

Question 23 of 40 Quiz ID: q23

In a cache entry, what is the purpose of the 'Valid' bit?

To indicate the data is correct and hasn't been corrupted

To indicate that the entry contains a meaningful address and data

To lock the entry so it cannot be replaced

To mark the entry as the most recently used

Question 24 of 40 Quiz ID: q24

Which portion of a memory address is used to select which set in a set-associative cache the block could be in?

The Tag

The Index

The Block Offset

The Byte Offset

Question 25 of 40 Quiz ID: q25

What type of cache miss is unavoidable because it is the first access to a block?

Capacity Miss

Conflict Miss

Compulsory Miss

Coherence Miss

Question 26 of 40 Quiz ID: q26

What type of cache miss occurs when the cache is not large enough to hold all the blocks needed during program execution?

Compulsory Miss

Conflict Miss

Capacity Miss

Structural Miss

Question 27 of 40 Quiz ID: q27

The strategy of bringing data into the cache before it is actually referenced by the processor is called:

Buffering

Pipelining

Prefetching

Speculative execution

Question 28 of 40 Quiz ID: q28

Which component is primarily responsible for translating a programmer's view of memory (virtual address) into the actual physical address in RAM?

The Cache Controller

The Memory Bus

The Memory Management Unit (MMU)

The Direct Memory Access (DMA) Controller

Question 29 of 40 Quiz ID: q29

In the hierarchy for a personal mobile device, which level typically has an access time of around 1 nanosecond?

Level 1 (L1) Cache

Level 2 (L2) Cache

Main Memory (DRAM)

Flash Storage

Question 30 of 40 Quiz ID: q30

What is the primary trade-off that the memory hierarchy is designed to manage?

Speed vs. Volatility

Speed vs. Cost vs. Capacity

Cost vs. Power Consumption

Capacity vs. Physical Size

Question 31 of 40 Quiz ID: q31

Which bus carries the control signals that indicate whether a read or write operation is to be performed?

Address Bus

Data Bus

Control Bus

System Bus

Question 32 of 40 Quiz ID: q32

In the Autoincrement addressing mode `(R2)+`, what happens after the register is used as an address?

The register is decremented

The register is incremented

The data at the address is incremented

The program counter is incremented

Question 33 of 40 Quiz ID: q33

A 'dirty' bit in a cache is used to indicate what?

The block is invalid

The block has been modified since being read from memory

The block is the least recently used

The block contains an error

Question 34 of 40 Quiz ID: q34

Which memory technology is primarily used for the 'Secondary Storage' level in a traditional memory hierarchy?

SRAM

DRAM

Magnetic Disk (Hard Drive)

EEPROM

Question 35 of 40 Quiz ID: q35

What is the key characteristic of a 'volatile' memory?

It can only be read, not written to

It loses its contents when power is removed

It has a very slow access time

It is extremely expensive per bit

Question 36 of 40 Quiz ID: q36

In the context of cache addressing, what are the 'Tag' bits used for?

To determine the byte offset within a block

To select which set to look in

To uniquely identify which main memory block is stored in the cache frame

To check the valid bit

Question 37 of 40 Quiz ID: q37

Which of these is NOT a common goal of the memory hierarchy?

To reduce the effective memory access time

To reduce the overall cost of the memory system

To make the main memory appear infinitely large

To eliminate the need for main memory (DRAM)

Question 38 of 40 Quiz ID: q38

A 'write-through' cache policy immediately writes data to:

The L2 cache

The main memory

The register file

The disk

Question 39 of 40 Quiz ID: q39

The performance of a memory hierarchy is most directly improved by having a:

High miss rate

High hit rate

Large miss penalty

Small cache size

Question 40 of 40 Quiz ID: q40

What problem does a 'victim cache' help to solve?

Compulsory misses

Capacity misses

Conflict misses

Coherence misses

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