Mock Quiz Hub

Recent Updates

Added: OS Mid 1 Quiz

Added: OS Mid 2 Quiz

Added: OS Lab 1 Quiz

Check back for more updates!

Time: 00:00

Quiz

Navigate through questions using the controls below

0%

Question 1 of 40 Quiz ID: q1

In RV32, why is it a challenge to load a 32-bit immediate value into a register with a single instruction?

Because all instructions are only 32 bits wide, leaving limited space for the opcode and a large immediate value

Because the immediate field is only 5 bits wide in all instruction formats

Because registers can only hold values up to 2^16

Because the opcode must be at least 16 bits long

Question 2 of 40 Quiz ID: q2

Which RISC-V instruction format is primarily used for arithmetic operations that involve three registers?

I-type

S-type

R-type

U-type

Question 3 of 40 Quiz ID: q3

What is the purpose of the 'funct3' and 'funct7' fields in RISC-V instruction encoding?

They specify the destination register for the operation

They hold the immediate value for I-type instructions

They extend the opcode to specify the exact operation to be performed (e.g., add vs. sub)

They indicate the memory address for load/store operations

Question 4 of 40 Quiz ID: q4

An instruction with the opcode '0010011' likely belongs to which format and type of instruction?

S-type, store instruction

I-type, immediate instruction

R-type, register instruction

U-type, upper immediate instruction

Question 5 of 40 Quiz ID: q5

What is the key difference between the 'lw' and 'lb' instructions regarding the loaded data?

'lw' loads a word (32 bits) while 'lb' loads a byte (8 bits) and sign-extends it to 32 bits

'lw' can only load from aligned addresses, while 'lb' can load from any address

'lw' uses the S-type format, while 'lb' uses the I-type format

'lw' requires two register operands, while 'lb' requires only one

Question 6 of 40 Quiz ID: q6

The 'lui' (Load Upper Immediate) instruction is crucial for building large constants. What does it do?

It loads a 20-bit immediate value into the lower 20 bits of the destination register, setting the upper 12 bits to zero

It loads a 12-bit immediate value into the destination register and sign-extends it

It loads a 20-bit immediate value into the upper 20 bits of the destination register, setting the lower 12 bits to zero

It adds a 20-bit immediate value to the program counter (PC)

Question 7 of 40 Quiz ID: q7

Which pseudo-instruction sequence would correctly implement 'mv s1, s2' (copy register s2 to s1)?

sub s1, s2, x0

addi s1, s2, 0

xor s1, s2, x0

ori s1, s2, 0

Question 8 of 40 Quiz ID: q8

What is the fundamental architectural difference between Von Neumann and Harvard architectures?

Von Neumann has a single memory space for data and code, while Harvard has separate memories

Harvard architecture is faster because it uses more registers

Von Neumann uses a stack-based model, while Harvard uses a register-based model

Harvard architecture cannot execute code from data memory

Question 9 of 40 Quiz ID: q9

In the context of memory addressing, what is placed on the address bus during a read operation?

The data word to be written to memory

The opcode of the instruction being executed

The location (address) of the data to be accessed

The contents of the program counter (PC)

Question 10 of 40 Quiz ID: q10

What is the primary purpose of the 'auipc' (Add Upper Immediate to PC) instruction?

To perform a conditional branch based on a register value

To jump to an absolute address stored in a register

To form a PC-relative address for a jump or data access

To load a constant into the upper bits of a register

Question 11 of 40 Quiz ID: q11

How is the 'la' (Load Address) pseudo-instruction typically expanded by the assembler?

lui rd, symbol[31:12]

auipc rd, symbol[31:12] followed by addi rd, rd, symbol[11:0]

lui rd, symbol[31:12] followed by addi rd, rd, symbol[11:0]

jalr rd, symbol(rs1)

Question 12 of 40 Quiz ID: q12

A B-type instruction like 'beq' changes the program flow based on a register comparison. How does it calculate the target address?

Target = rs1 + (sign-extended immediate)

Target = PC + (sign-extended immediate << 1)

Target = immediate << 12

Target = absolute address in rs2

Question 13 of 40 Quiz ID: q13

Why is the immediate value in a B-type instruction encoded in the seemingly scrambled order [12|10:5|4:1|11]?

To make the instruction format unique and harder to decode

To maximize the range of the branch offset

To align the bit positions with those in other instruction types (S-type) to simplify hardware decoding

To allow for a larger funct3 field

Question 14 of 40 Quiz ID: q14

What is the range of addresses a B-type branch instruction can reach from the current PC?

± 2^10 bytes

± 2^11 bytes

± 2^12 bytes

± 2^13 bytes

Question 15 of 40 Quiz ID: q15

What is the key functional difference between the 'jal' and 'jalr' instructions?

'jal' is for conditional jumps, 'jalr' is for unconditional jumps

'jal' uses PC-relative addressing, 'jalr' uses base register + offset addressing

'jal' does not link (save return address), 'jalr' always links

'jal' can only jump forwards, 'jalr' can jump backwards

Question 16 of 40 Quiz ID: q16

How is the 'ret' (return from function) pseudo-instruction implemented?

jalr x0, x0, 0

jalr x0, x1, 0

beq x0, x0, -4

jal x0, 0

Question 17 of 40 Quiz ID: q17

What is the purpose of the 'linking' aspect in the 'jal' and 'jalr' instructions?

It links object files together during assembly

It calculates the address of the next instruction (PC+4) and writes it to register rd

It creates a chain of function calls for debugging

It checks if the jump target is valid and linked into the program

Question 18 of 40 Quiz ID: q18

Which two instructions are combined to jump to an arbitrary 32-bit absolute address?

lui and jal

auipc and jalr

lui and jalr

jal and jalr

Question 19 of 40 Quiz ID: q19

What is the effective range of a jump using the J-type 'jal' instruction?

± 1 MiB

± 2 MiB

± 4 MiB

± 1 MB

Question 20 of 40 Quiz ID: q20

The Stored Program Concept is a fundamental principle of most modern computers. What does it mean?

Programs must be stored in non-volatile memory like ROM

Instructions and data are stored in the same read-write memory and can be manipulated alike

The program counter stores the address of the next instruction

All data must be loaded into registers before being operated on

Question 21 of 40 Quiz ID: q21

Which bitwise operation and immediate value would flip the case of an ASCII letter (e.g., 'A' to 'a')?

ORI with 0x20

XORI with 0x20

ANDI with 0xDF

SLLI by 5

Question 22 of 40 Quiz ID: q22

What is the purpose of the 'sext.w' (Sign Extend Word) pseudo-instruction?

To extend a 16-bit immediate value to 32 bits

To extract the lower 32 bits from a 64-bit value in RV64

To sign-extend the lower 32 bits of a register to the full register width

To convert a signed integer to an unsigned integer

Question 23 of 40 Quiz ID: q23

Which instruction sequence would set register 't0' to 1 if register 'a0' is equal to zero?

sltiu t0, a0, 1

xori t0, a0, 0

addi t0, a0, -1

sltu t0, x0, a0

Question 24 of 40 Quiz ID: q24

What is the valid range for the 12-bit immediate operand in an 'addi' instruction?

0 to 4095

-2048 to 2047

-4096 to 4095

0 to 65535

Question 25 of 40 Quiz ID: q25

Which addressing mode is used by the 'lw rd, offset(rs1)' instruction?

PC-relative addressing

Register indirect with displacement

Direct addressing

Immediate addressing

Question 26 of 40 Quiz ID: q26

What is the primary hazard of allowing data and instructions to share the same memory (Von Neumann architecture)?

It is slower than Harvard architecture

It is more expensive to implement

A program error can overwrite instructions, causing a crash

It requires more complex compiler design

Question 27 of 40 Quiz ID: q27

The 'bge' (Branch if Greater Than or Equal) instruction interprets its operands as:

Unsigned integers

Signed integers

Floating-point numbers

It is defined by the 'funct3' field

Question 28 of 40 Quiz ID: q28

What is the role of the 'opcode' field in a RISC-V instruction?

It specifies the destination register

It specifies the base instruction format (R, I, S, etc.) and the general operation

It holds the immediate value for the instruction

It determines if the instruction accesses memory

Question 29 of 40 Quiz ID: q29

Which instruction would be most efficient for setting register 'a0' to the constant value 0x12345000?

addi a0, x0, 0x12345000

lui a0, 0x12345

lui a0, 0x12345 followed by addi a0, a0, 0x000

ori a0, x0, 0x5000

Question 30 of 40 Quiz ID: q30

In the instruction 'sw rs2, offset(rs1)', which fields in the S-type format hold the components of the 12-bit 'offset'?

imm[11:5] and rs2

imm[11:5] and imm[4:0]

funct7 and funct3

rs1 and rd

Question 31 of 40 Quiz ID: q31

What does the 'neg' (Negate) pseudo-instruction do, and how is it implemented?

Ones' complement: xori rd, rs, -1

Twos' complement: sub rd, x0, rs

Logical NOT: andi rd, rs, 0

Subtract from zero: addi rd, x0, 0 followed by sub rd, rd, rs

Question 32 of 40 Quiz ID: q32

Why must instructions be aligned on specific address boundaries (e.g., 4-byte for 32-bit instructions)?

To make the program counter simpler

To save space in the instruction cache

To simplify the hardware that fetches instructions from memory

It is a requirement of the RISC-V assembly language syntax

Question 33 of 40 Quiz ID: q33

Which of these is NOT a valid reason for RISC-V's choice of variable immediate encoding across formats?

To keep instruction length fixed at 32 bits

To maximize the range of addresses and constants that can be used

To simplify the instruction decoder by having a uniform immediate field

To allow the immediate bits to be located in the same positions as register fields in other formats

Question 34 of 40 Quiz ID: q34

What is the function of the 'funct7' field in an R-type instruction like 'sub'?

It specifies the second source register

It distinguishes between different operations that share the same opcode and funct3, like 'add' and 'sub'

It holds the shift amount for shift instructions

It specifies the destination register

Question 35 of 40 Quiz ID: q35

The 'jalr' instruction's target address calculation has one important constraint. What is it?

The target address must be word-aligned

The immediate offset must be zero

The base register (rs1) must be the stack pointer

The target address must be within the same 4KiB page as the PC

Question 36 of 40 Quiz ID: q36

Which pair of instructions is crucial for implementing position-independent code (PIC) in RISC-V?

lui and addi

auipc and jalr

beq and bne

jal and ret

Question 37 of 40 Quiz ID: q37

What is the purpose of the 'nop' (No Operation) instruction, and what is its canonical encoding in RISC-V?

To stall the pipeline; addi x0, x0, 0

To clear the interrupt flag; xori x0, x0, 0

To flush the cache; lui x0, 0

To waste a cycle; jal x0, 0

Question 38 of 40 Quiz ID: q38

In the context of the lecture's loop example ('bne t0, t1, repeat'), what is the role of the 'ret' instruction?

It returns from the 'main' function to the operating system or runtime environment

It breaks out of the loop when the condition is met

It resets the program counter to the start of the program

It transfers control to the exception handler

Question 39 of 40 Quiz ID: q39

Which mask and operation would set bits 2 and 4 (0-indexed from LSB) of a register to 1, regardless of their previous state?

ORI with mask 0b00010100 (0x14)

ANDI with mask 0b11101011 (0xFFFFFFEB)

XORI with mask 0b00010100 (0x14)

SLLI by 2 and then by 4

Question 40 of 40 Quiz ID: q40

What is the core trade-off expressed in the RISC-V ISA design regarding instruction encoding?

Simplicity of hardware decode vs. richness of instruction capabilities

Execution speed vs. power consumption

Code density vs. number of available registers

Support for floating-point vs. integer operations

Quiz Summary

Review your answers before submitting

40

Total Questions

0

Answered

40

Remaining

00:00

Time Spent

Question 1 of 40

!

Quiz

Quiz Summary

Confirm Submission