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Question 1 of 40 Quiz ID: q1

What is the fundamental challenge that necessitates the use of different instruction formats in RISC-V?

The need to support complex CISC operations

The limited 32-bit instruction word size in RV32

The requirement for variable-length instructions

The lack of enough opcode bits

Question 2 of 40 Quiz ID: q2

Which RISC-V instruction format is used for arithmetic operations that utilize three registers?

I-type

R-type

S-type

U-type

Question 3 of 40 Quiz ID: q3

An I-type instruction's immediate field is how many bits wide?

5 bits

7 bits

12 bits

20 bits

Question 4 of 40 Quiz ID: q4

What is the primary purpose of the U-type instruction format?

To store values to memory

To handle conditional branches

To load a 20-bit immediate value into the upper bits of a register

To perform jump and link operations

Question 5 of 40 Quiz ID: q5

How is the `lui t1, 0x70070` instruction correctly described?

It adds 0x70070 to the program counter.

It loads the value 0x70070 into the lower 20 bits of register t1.

It loads the value 0x70070 << 12 into register t1.

It is an illegal instruction because the immediate is too large.

Question 6 of 40 Quiz ID: q6

Why can't a single RISC-V instruction load an arbitrary 32-bit immediate value (e.g., 0x700707FF) into a register?

The opcode field is too large, leaving no room for the immediate.

The instruction word is only 32 bits and must also contain the opcode and register fields.

RISC-V only supports 16-bit immediates.

It would require a 64-bit instruction set.

Question 7 of 40 Quiz ID: q7

What two instructions are typically used to load the 32-bit value 0x000707FF into register t0?

lui t0, 0x7; ori t0, t0, 0x7FF

lui t0, 0x70; addi t0, t0, 0x7FF

addi t0, zero, 0x707FF

lui t0, 0x707; addi t0, t0, 0xFF

Question 8 of 40 Quiz ID: q8

How can the value 0x0000FFFF be loaded into a register using `lui` and `addi`?

lui t0, 0x0; addi t0, t0, 0xFFFF

lui t0, 0x1; addi t0, t0, -1

lui t0, 0xFFFF; addi t0, t0, 0x0

It cannot be done because 0xFFFF is too large for addi.

Question 9 of 40 Quiz ID: q9

What is a primary real-world consideration that leads to the design of a more complex ISA like RISC-V instead of a simpler one?

Making assembly programming easier for humans

Maximizing code density and performance for benchmark programs

Minimizing the number of instruction formats

Ensuring all instructions are the same length

Question 10 of 40 Quiz ID: q10

What is the purpose of a pseudo-instruction in assembly language?

It is a placeholder for an instruction the hardware will implement in the future.

It is a complex instruction that is executed directly by the microprocessor.

It is an intuitive instruction for the programmer that the assembler translates into one or more base instructions.

It is an instruction that performs an operation on pseudo-registers.

Question 11 of 40 Quiz ID: q11

Which base instruction is the `nop` (No Operation) pseudo-instruction typically equivalent to?

addi x0, x0, 0

sub x0, x0, x0

lui x0, 0

jal x0, 0

Question 12 of 40 Quiz ID: q12

What is a key difference between registers and main memory from a programmer's perspective?

Registers are addressed by name, while memory is addressed by location.

Memory is faster than registers.

There is more register space than memory space.

Registers are viewed as a contiguous array, while memory is not.

Question 13 of 40 Quiz ID: q13

In the instruction `lw x5, 4(x10)`, what is the role of register x10?

It is the destination register where the loaded word will be stored.

It is the source register containing the data to be stored.

It is the base address register used to calculate the effective memory address.

It is the register that holds the immediate offset value.

Question 14 of 40 Quiz ID: q14

Which instruction format is used for the `sw` (Store Word) instruction?

R-type

I-type

S-type

U-type

Question 15 of 40 Quiz ID: q15

In the S-type format, why is the 12-bit immediate value split into two non-adjacent fields (imm[11:5] and imm[4:0])?

To confuse disassemblers

To make the encoding more secure

To allow the `rs2` and `rs1` register fields to stay in the same positions as in the R-type format

Because there are not enough contiguous bits available

Question 16 of 40 Quiz ID: q16

What is the advantage of using the `auipc` (Add Upper Immediate to PC) instruction?

It allows for faster arithmetic calculations.

It enables position-independent code by calculating addresses relative to the current program counter.

It is used to implement system calls.

It simplifies the decoding of jump instructions.

Question 17 of 40 Quiz ID: q17

How is the `la a0, A` (Load Address) pseudo-instruction typically expanded?

lui a0, %hi(A); addi a0, a0, %lo(A)

addi a0, zero, A

lw a0, 0(A)

auipc a0, %pcrel_hi(A); addi a0, a0, %pcrel_lo(A)

Question 18 of 40 Quiz ID: q18

If `auipc a0, 0x2` is executed at PC = 0x000000d8, what value will be placed in register a0?

0x00000002

0x00002000

0x000020d8

0x000002d8

Question 19 of 40 Quiz ID: q19

Which RISC-V instruction type is used for conditional branch instructions like `beq`?

R-type

I-type

S-type

B-type

Question 20 of 40 Quiz ID: q20

In the B-type format, how is the 13-bit immediate offset encoded?

It is stored in a single contiguous field.

It is split into five separate fields.

It is split into imm[12], imm[10:5], imm[4:1], and imm[11] and placed in specific bit positions.

It is not an immediate offset but a register address.

Question 21 of 40 Quiz ID: q21

What does the instruction `beq rs1, rs2, imm` do?

It adds the immediate to rs1 and stores the result in rs2.

It branches to the address in rs1 if rs2 equals zero.

It adds the immediate to the PC if the value in rs1 is equal to the value in rs2.

It stores the value of rs1 to the memory address in rs2 offset by imm.

Question 22 of 40 Quiz ID: q22

What is the size of the opcode field in all RISC-V base instructions?

3 bits

5 bits

7 bits

12 bits

Question 23 of 40 Quiz ID: q23

The `funct3` field in RISC-V instructions is primarily used for:

Specifying the destination register

Specifying the shift amount for immediate instructions

Further specifying the operation to be performed, often as a sub-opcode

Holding the upper bits of a large immediate value

Question 24 of 40 Quiz ID: q24

Which field is common to both R-type and I-type instructions?

funct7

rs2

imm[11:0]

rs1

Question 25 of 40 Quiz ID: q25

What is the maximum positive value that can be represented in the 12-bit immediate field of an I-type instruction before sign-extension?

1023

2047

4095

8191

Question 26 of 40 Quiz ID: q26

The `jal` (Jump and Link) instruction uses which format?

J-type

I-type

U-type

B-type

Question 27 of 40 Quiz ID: q27

What problem does the U-type instruction format directly help solve?

The need for more than 32 registers

The difficulty of loading large constants or addresses into registers

The complexity of decoding branch instructions

The slow speed of memory access

Question 28 of 40 Quiz ID: q28

In the context of memory access, what does the term 'byte addressable' mean?

Each memory address holds one byte (8 bits) of data.

Each memory address holds one word (32 bits) of data.

Addresses are stored in bytes.

The address bus is 8 bits wide.

Question 29 of 40 Quiz ID: q29

What is the key difference between `lh` (Load Halfword) and `lhu` (Load Halfword Unsigned)?

`lh` loads 16 bits, `lhu` loads 32 bits.

`lh` sign-extends the loaded value to 32 bits, while `lhu` zero-extends it.

`lh` uses the I-type format, `lhu` uses the S-type format.

`lh` is for data, `lhu` is for instructions.

Question 30 of 40 Quiz ID: q30

Why might an assembler generate different immediate values for two identical `la a0, A` pseudo-instructions in the same program?

It is a bug in the assembler.

The symbol 'A' has moved in memory.

The instructions are at different program counter (PC) addresses, so the offset from the PC to 'A' is different for each.

The assembler randomizes the code for security.

Question 31 of 40 Quiz ID: q31

What is the effective address calculated by the instruction `sw x5, 4(x10)`?

The value in x5 plus 4

The value in x10 plus 4

The value 4

The value in x5

Question 32 of 40 Quiz ID: q32

Which of the following is NOT a reason for the complexity of RISC-V's instruction encoding?

The desire to keep the instruction length fixed at 32 bits

The need to support a large number of registers (32)

The goal of simplifying the hardware decoder by keeping register fields in consistent positions

The requirement to make assembly code instantly readable by humans

Question 33 of 40 Quiz ID: q33

What is the purpose of the `funct7` field in the R-type instruction format?

To specify the second source register

To provide additional bits to specify the operation, often distinguishing between arithmetic and logical shifts

To hold the upper bits of the immediate value for I-type instructions

To specify the branch condition for B-type instructions

Question 34 of 40 Quiz ID: q34

What is the maximum branch offset range achievable with the 13-bit immediate in a B-type instruction?

±256 bytes

±1024 bytes

±4096 bytes

±8192 bytes

Question 35 of 40 Quiz ID: q35

The `ret` (Return) pseudo-instruction is equivalent to:

jalr x0, 0(x1)

jalr x0, x1, 0

jr x1

addi x0, x0, 0

Question 36 of 40 Quiz ID: q36

Which instruction would you use to load a byte from memory and ensure the upper 24 bits of the destination register are cleared?

lb

lbu

lh

lw

Question 37 of 40 Quiz ID: q37

What is the role of the `rd` field in most RISC-V instruction formats?

It specifies the register containing the second source operand.

It specifies the register where the result of the operation will be written.

It holds part of the immediate value for memory instructions.

It determines the type of operation to be performed.

Question 38 of 40 Quiz ID: q38

The immediate value in a U-type instruction is positioned in the instruction word:

In the least significant bits (bits [11:0])

In the most significant bits (bits [31:12])

Split around the register fields

It does not have an immediate value

Question 39 of 40 Quiz ID: q39

What is the fundamental trade-off illustrated by the need for pseudo-instructions like `li`?

Speed vs. Cost

Hardware simplicity vs. Programmer convenience

Memory size vs. Register count

Power consumption vs. Heat output

Question 40 of 40 Quiz ID: q40

Which characteristic is common to all instruction formats in the RISC-V base ISA?

They all have an `rs2` field.

They all have a 12-bit immediate field.

They are all exactly 32 bits long.

They all use the `funct7` field.

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