Quiz

Which section of a microprocessor is primarily responsible for fetching instructions from program memory?

A major concern for processor design in mobile phones, compared to laptops, is:

The abstraction layer that defines the native data types, instructions, and registers available to a programmer is known as the:

A processor with a large number of dedicated hardware co-processors and a complex set of instructions is characteristic of a:

Which of the following is a key characteristic of a RISC architecture?

The x86-64 ISA, widely used in modern desktops and laptops, originated from:

What is a defining feature of the RISC-V ISA that differentiates it from many other ISAs?

In the RISC-V modular scheme, what does the 'M' standard extension provide?

An RV32IMAFD ISA is equivalent to:

What is the primary purpose of the RISC-V 'C' extension?

A fundamental challenge in encoding instructions for a 32-bit RISC architecture like RV32I is:

Which RISC-V instruction format is used for register-register arithmetic operations like `add` and `xor`?

How many different registers can be specified in a single RISC-V instruction using the 5-bit rs1, rs2, and rd fields?

In the R-type instruction format, the 'funct7' and 'funct3' fields are primarily used to:

What is the key difference between a logical right shift (srl) and an arithmetic right shift (sra)?

For the instruction `add x5, x6, x7`, what is the value of the 'funct7' field in its machine code encoding?

Which RISC-V instruction format is specifically designed for instructions that use a constant immediate value and one source register, such as `addi`?

What is the range of the 12-bit immediate value in an I-type instruction like `addi` after it is sign-extended to 32 bits?

The instruction `andi x5, x6, 4` performs a bitwise AND between the value in register x6 and the immediate value 4. How is the immediate value 4 represented in the 12-bit 'imm' field of this I-type instruction?

For the instruction `andi x5, x6, -4`, what is the correct 12-bit two's complement encoding of the immediate value -4?

In RISC-V, which register is hardwired to always contain the value zero?

Which RISC-V register is conventionally used to hold the return address for a function call?

Which set of registers (x12-x17) is conventionally used for what purpose in RISC-V?

What is the operation performed by the instruction `srai s3, s4, 31`?

The instruction `lw s7, 0x2C(t1)` will:

Which instruction is used to transfer control to an instruction address stored in a register?

The RISC-V instruction `li s1, 0xABCDEF12` is most likely:

Which instruction format is used for store operations like `sw` (store word)?

The U-type instruction format provides a 20-bit immediate value that is placed:

Which instruction is crucial for building function calls, as it saves the return address to the `ra` register?

A good ISA should last through many implementations. This promotes:

The argument that a programmer only needs the assembly instructions and register map, not hardware details, assumes the ISA provides a complete:

The 'A' standard extension in RISC-V provides instructions for:

The RISC-V 'F' and 'D' extensions are related to:

A processor designed for a low-power embedded system might use the RV32E variant because it:

What is the primary functional difference between the I-type `slli` (shift left logical immediate) and the R-type `sll` (shift left logical) instruction?

The `beq` (branch if equal) instruction in RISC-V uses which instruction format?

The `lui` (load upper immediate) instruction is primarily used to:

Which pseudoinstruction would likely be expanded into an `xori` instruction with all ones?

The ability to discover available ISA extensions in a RISC-V core by reading the 'misa' CSR demonstrates the importance of:

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