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Question 1 of 40 Quiz ID: q1

According to the syllabus, which of the following is a primary learning outcome for the Computer Architecture module?

Design and fabricate semiconductor components

Develop a simple microprocessor with a limited instruction set

Write and optimize high-level language compilers

Troubleshoot and repair commercial computer hardware

Question 2 of 40 Quiz ID: q2

The recommended textbook 'Computer Architecture: A Quantitative Approach' by Hennessy and Patterson covers several key areas. Which of the following is NOT one of them?

Instruction Set Architecture (ISA)

Domain specific architectures

Quantum computing algorithms

Memory Hierarchy

Question 3 of 40 Quiz ID: q3

What is the fundamental difference between Computer Architecture and Computer Organization?

Architecture deals with software, Organization deals with hardware.

Architecture is the programmer's view (ISA), Organization is the designer's view (internal implementation).

Architecture is about performance, Organization is about cost.

They are synonymous terms and can be used interchangeably.

Question 4 of 40 Quiz ID: q4

In the context of the 'nano-processor' example, what major performance enhancement technique was identified as missing from its single-cycle design?

Caching

Pipelining

Multithreading

Speculative execution

Question 5 of 40 Quiz ID: q5

Which register is solely responsible for holding the memory address of the next instruction to be fetched?

Instruction Register (IR)

Accumulator (A)

Status Register

Program Counter (PC)

Question 6 of 40 Quiz ID: q6

After an instruction is fetched from memory, where is it stored within the CPU for decoding and execution?

Program Counter (PC)

Accumulator (A)

Instruction Register (IR)

General Purpose Register (e.g., t1)

Question 7 of 40 Quiz ID: q7

What is a key architectural difference between a Microprocessor and a Microcontroller?

Microcontrollers are always faster than microprocessors.

Microprocessors integrate most I/O functions into the same package as the CPU, unlike microcontrollers.

Microcontrollers integrate most I/O functions into the same package as the CPU, unlike microprocessors.

Microprocessors cannot be used in embedded systems.

Question 8 of 40 Quiz ID: q8

In the programming hierarchy, what level sits directly above 'Machine (ISA)' and directly below 'High-Level Language'?

Digital Logic

Control

Assembly Language

System Software

Question 9 of 40 Quiz ID: q9

Why is knowledge of Assembly Language still considered useful for programmers and computer engineers?

It is the most portable language across different architectures.

It is the easiest language for writing complex algorithms.

It allows for producing fast code and utilizing advanced CPU features not accessible from high-level languages.

All modern software is ultimately written in Assembly.

Question 10 of 40 Quiz ID: q10

What is the primary function of the Arithmetic Logic Unit (ALU)?

To manage the fetch-decode-execute cycle

To store the results of operations in the Program Counter

To perform arithmetic and logic operations on data

To decode instructions fetched from memory

Question 11 of 40 Quiz ID: q11

In a typical computer system overview, what is the role of the 'Bus'?

To execute instructions

To store the operating system

To interconnect the CPU, memory, and I/O devices by transferring data between them

To convert AC power to DC power for the components

Question 12 of 40 Quiz ID: q12

Which step in the instruction execution sequence immediately follows 'Fetch next instruction from memory'?

Execute the instruction

Change PC to point to the next instruction

Determine the type of instruction

Fetch data from memory if needed

Question 13 of 40 Quiz ID: q13

What does the RISC-V 'la a0, A' instruction (Load Address) accomplish?

It loads the value stored at memory address A into register a0.

It loads the immediate value 'A' into register a0.

It calculates and loads the memory address of variable 'A' into register a0.

It adds the value in register a0 to the address of A.

Question 14 of 40 Quiz ID: q14

In RISC-V, what is the purpose of the 'zero' register (x0)?

It indicates an error has occurred when its value changes.

It is used for temporary storage of calculations.

It always contains the value 0 and writes to it are discarded.

It holds the return address for function calls.

Question 15 of 40 Quiz ID: q15

Which RISC-V instruction type is characterized by having fields for two source registers and one destination register?

S-type (Store)

I-type (Immediate)

R-type (Register)

J-type (Jump)

Question 16 of 40 Quiz ID: q16

What is the key conceptual purpose of an Instruction Set Architecture (ISA)?

To define the exact transistor-level layout of a processor.

To act as a layer of abstraction between the hardware and the software, defining what the programmer needs to know.

To specify the clock speed and power consumption of a processor.

To determine the physical packaging and cooling requirements of a chip.

Question 17 of 40 Quiz ID: q17

According to the lecture, what is a significant missing component in the nano-processor regarding its interaction with the outside world?

An Arithmetic Logic Unit (ALU)

A complex instruction decoder

A memory hierarchy and cache system

A multi-stage pipeline

Question 18 of 40 Quiz ID: q18

In the FLAG/STATUS register, what is the typical purpose of the 'Zero' bit?

It indicates an arithmetic overflow has occurred.

It is set to 1 if the result of the last operation was zero.

It disables all maskable interrupts when set.

It signifies the processor is in supervisor mode.

Question 19 of 40 Quiz ID: q19

What is the role of the 'Control Unit' in the 2nd-level view of a computer?

To perform arithmetic calculations

To act as fast storage for intermediate results

To generate the control signals that coordinate the activities of the ALU, registers, and other components

To physically connect the address and data buses

Question 20 of 40 Quiz ID: q20

The process of 'Assembling' primarily involves:

Linking multiple object files into a single executable.

Converting high-level language code into assembly code.

Converting mnemonic assembly instructions and symbols into binary machine code.

Loading the executable program into memory for execution.

Question 21 of 40 Quiz ID: q21

Which of the following is NOT a common metric for evaluating different classes of computers (e.g., servers, embedded)?

Reliability

Cost

The brand of the CPU

Energy consumption

Question 22 of 40 Quiz ID: q22

In the RISC-V ISA, which register is conventionally used to hold the first argument to a function and its return value?

sp (x2, Stack Pointer)

a0 (x10)

ra (x1, Return Address)

t0 (x5)

Question 23 of 40 Quiz ID: q23

What is the fundamental operational difference between the 'lw' (Load Word) and 'sw' (Store Word) instructions?

'lw' moves data from a register to memory, 'sw' moves data from memory to a register.

'lw' moves data from memory to a register, 'sw' moves data from a register to memory.

Both move data between registers, but 'lw' is for words and 'sw' is for bytes.

'lw' is for arithmetic, 'sw' is for logic operations.

Question 24 of 40 Quiz ID: q24

The 'beq' (Branch if Equal) instruction is an example of what type of instruction flow control?

Unconditional jump

Conditional branch

Function call

Exception trap

Question 25 of 40 Quiz ID: q25

What is the primary challenge that a memory hierarchy (including caches) is designed to address?

The high cost of magnetic hard disk drives

The difficulty of programming parallel systems

The speed gap between the fast processor and the slower main memory (DRAM)

The limited number of registers available in an ISA

Question 26 of 40 Quiz ID: q26

In the context of processor design, what does the term 'pipelining' refer to?

Using multiple independent processor cores on a single chip.

Overlapping the stages of instruction processing (fetch, decode, execute) to improve throughput.

Increasing the clock speed to make each instruction execute faster.

Adding more general-purpose registers to the CPU.

Question 27 of 40 Quiz ID: q27

Which tool mentioned in the lecture is a web-based simulator specifically for the RISC-V architecture?

Ripes

WebRiscV

Verilog

FPGA development suites

Question 28 of 40 Quiz ID: q28

What is the purpose of the 'Stack Pointer' (sp, x2) register in RISC-V?

To point to the next instruction to be executed.

To hold the result of arithmetic operations.

To point to the top of the stack in memory, used for saving register context during function calls.

To hold a global variable.

Question 29 of 40 Quiz ID: q29

The 'jal' (Jump and Link) instruction is crucial for implementing what programming construct?

Arithmetic loops

Function or procedure calls

Conditional if-else statements

Data movement between registers

Question 30 of 40 Quiz ID: q30

Which component in the high-level computer view is primarily responsible for storing the program instructions and data that are currently in use?

CPU

Bus

Memory

Input/Output Devices

Question 31 of 40 Quiz ID: q31

What is the role of the 'Instruction Decoder' block in a microprocessor?

To fetch the instruction from memory.

To perform the arithmetic calculation specified by the instruction.

To interpret the binary opcode in the IR and activate the appropriate control signals for other components.

To hold the address of the next instruction.

Question 32 of 40 Quiz ID: q32

In a multi-stage pipeline like the SweRV EH1 core, what is a potential hazard that must be managed?

Voltage hazard

Data hazard (e.g., a later instruction needs the result of an earlier one that's still in the pipeline)

Heat hazard

Physical size hazard

Question 33 of 40 Quiz ID: q33

The 'Amdahl's Law' mentioned in the syllabus is most relevant to evaluating the potential speedup from which performance enhancement technique?

Increasing the clock speed

Adding an SSD instead of an HDD

Pipelining or parallel processing

Adding more registers

Question 34 of 40 Quiz ID: q34

What is the key difference between a 'RISC' and a 'CISC' architecture at the ISA level?

RISC has more complex instructions than CISC.

CISC has a large and variable instruction set, while RISC has a smaller, simpler, fixed-length set.

RISC is only for embedded systems, CISC is for desktops.

CISC processors cannot be pipelined effectively.

Question 35 of 40 Quiz ID: q35

Which of the following is a primary advantage of using a Hardware Description Language (HDL) like Verilog for computer architecture, as suggested in the lab tools?

It allows writing programs that run faster than in C++.

It enables the design, simulation, and implementation of digital hardware (like processors) before physical fabrication.

It is used to write the operating system kernel.

It is the primary language for programming FPGAs as if they were microcontrollers.

Question 36 of 40 Quiz ID: q36

What is the purpose of the 'System on Chip (SoC)' concept mentioned in the lecture?

To create a computer system using only a single type of chip.

To integrate all or most components of a computer (processor(s), memory, peripherals) onto a single integrated circuit.

To make software operating systems obsolete.

To refer to the primary CPU chip in any computer.

Question 37 of 40 Quiz ID: q37

In the RISC-V instruction 'addi t3, t1, -10', what is the role of the value '-10'?

It is a memory address.

It is an immediate value that is added to the contents of register t1.

It is the opcode for the subtraction operation.

It specifies the destination register number.

Question 38 of 40 Quiz ID: q38

Which bus in the 2nd-level computer view is typically unidirectional and carries the addresses generated by the CPU to memory and I/O devices?

Data Bus

Address Bus

Control Bus

I/O Bus

Question 39 of 40 Quiz ID: q39

What is the significance of the 'Harvard vs. Von Neumann' architectural difference?

It defines the number of cores in a processor.

It relates to how memory is organized: separate instruction/data memories (Harvard) vs. a unified memory (Von Neumann).

It determines the clock speed of the processor.

It specifies whether the processor is RISC or CISC.

Question 40 of 40 Quiz ID: q40

The 'LSU' (Load-Store Unit) in a complex processor pipeline like SweRV EH1 is primarily responsible for:

Fetching instructions from memory.

Decoding arithmetic instructions.

Handling all data transfers between the processor's registers and the main memory.

Managing the branch prediction logic.

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